Authored by Behzad Dehlaghi, Jaro Pristupa, Shayan Shahramian, and Tony Chan Carusone, University of Toronto; and Marco Dragic, Jim Quinn, CMC Microsystems.
This product includes a methodology document and a sample reference design. It is intended as an introduction to analog/RF design flow for the ST Microelectronics 28nm FD-SOI CMOS technology provided by ST through CMP.
The package includes:
- Step-by-step user-guide document
- Sample design with schematic, symbol, and layout views
- Test bench design with schematic and configuration views
- Post-layout simulation script that enables extraction and streamlined PLS flow
Table of Contents
- Introduction
- ST28nm FD-SOI Process Design Kit
- Setting Up the Design Kit
- ST28nm FD-SOI Libraries
- Analog IC Design Flow and Required Tools
- Corner Simulations
- Monte Carlo Simulation
- Layout versus Schematic (LVS)
- Design Rule Check (DRC)
- Post Layout Simulation (PLS)
- Design Submission to CMC
- Appendix I – PLS Extraction and Simulation Script
You may access this product if your university site has signed the 28nm FD SOI STMicroelectronics Non Disclosure Agreement. To find out if your university has signed this agreement, see the STMicroelectronics University List.
In addition to the NDA, access to the product is subject to the Network Security Requirements.
For more information contact our Licensing Administrator at licensing@cmc.ca or 613-530-4787.
