Characterization Report: ST 28 nm Bulk CMOS LP Process

This report authored by Prof. Sorin Voinigescu's group at the University of Toronto describes transistor test structures designed during the October 2011 to February 2012 period in the 8-metal version of the STMicroelectronics 28nm LP high-k metal gate CMOS process. The report includes layout design guidelines and measurement results. Measurements are compared with those performed in the same setup on STMicroelectronics 65nm GP CMOS devices.

  • Access to this report is subject to the ST 28nm NDA.
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Characterization Report: ST 28 nm Bulk CMOS LP Process

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