Prepared by Arthur Teimourian, IAESTE Intern at CMC Microsystems, Karlsruhe Institute of Technology (KIT), Germany.
The Design Workshop Technologies’ dw-2000 software (www.designw.com) provides users with an interface for creating physical layouts and verifying optical components using planar waveguide technology. When creating layouts, users must be aware of design rules that represent the verification part of dw-2000. The verification is performed by Design Rule Checking (DRC). However, performing a standard DRC on a large layout results in either huge time efforts to partition the layout manually or a software failure due to insufficient memory.
This application note describes fully automatic partitioning (FAP) code for the Design Rule Checking (DRC) verification phase in the dw-2000 software. The code reduces both processing time and memory requirements.
