Prepared by Moufid Radji, Master of Engineering candidate, McGill University, under co-supervision of Ricardo Izquierdo (UQÀM) and Anas A. Hamoui (McGill).
This application note describes a series of microfabrication steps aimed at handling and post-processing a small complementary metal–oxide–semiconductor (CMOS) die.
Common processing steps such as lithography or metal deposition are often a challenge with loose die. The starting point in the process is a bare, unpackaged die; to handle this small device (~310 um thick) the approach is to use a silicon support wafer (~520 um thick). The two critical processing steps when handling CMOS dice are lithography (using the dice themselves as a mask) and etching of the tight fitting cavity with Deep Reactive Ion Etching (DRIE). The die can be inserted into this cavity and handled with ease in further processing steps such as lithography, physical vapor deposition (PVD) or additional DRIE. This application uses the example of a TSMC CMOS-180nm chip, specifically TestChip 1.0 resulting from DreamWafer® research. This chip was processed to add an additional patterned metal layer on the front side as well as through-silicon vias (TSVs) on the backside.
This document is of particular interest to researchers who have access to microfabrication facilities in their university and want to further process millimeter-sized integrated circuits received from industrial partners.
All CMC Microsystem account holders with a Professor Research Subscription are authorized to access this application note. For more information contact Linda Dougherty at licensing@cmc.ca or 613-530-4787.
