Prepared by Mariusz E. Jarosz, Test and Packaging Engineer, CMC Microsystems.
This application note describes a method of modeling and verifying the performance of high-speed electrical traces on a printed circuit board (PCB), which is used as a test interface to a digital microelectronic device. The flow utilizes Allegro Design Flow Integration—a computer aided design (CAD) tool that may be used to export a PCB design file defined in Cadence Allegro PCB Editor Agilent Advanced Design System (ADS) Layout. Using this approach, the user may leverage the electromagnetic (EM) solving power of the ADS toolset to model the performance of the PCB design for high-frequency applications. Either the entire PCB design or a subset of selected nets may be exported and simulated. An example is given to analyze the bandwidth of a selected trace from a CMC test fixture for the Ceramic Quad Flat Pack (CQFP120) package, which was designed for use with the Verigy 93K system-on-chip (SOC) tester.
The application note is intended for designers preparing custom PCB-based Device Under Test interfaces (DUT boards) that must meet stringent signal speed and bandwidth specifications. As a prerequisite, you need basic understanding of transmission line theory, and working knowledge of CAD tools (Cadence Allegro and ADS Layout) and analysis tools (ADS Momentum, a planar electromagnetic simulator, and ADS HPEESofSIM, a circuit simulator). All the aforementioned tools are available to CMC clients.
All CMC Microsystem account holders with a Subscription are authorized to access this application note. For more information contact Linda Dougherty at licensing@cmc.ca or 613-530-4787.
