Prepared by Leonid Belostotski, Assistant Professor, Electrical and Computer Engineering, University of Calgary.
This application note describes the tests conducted to estimate the parasitics associated with flip-chip bonding of CMOS chips. Flip-chip bonding is a newer approach to package integrated circuits onto printed circuit boards. This approach has advantages over the conventional wire bonding packaging. Flip-chip bonding also affects the performance of spiral inductors by reducing their frequency of self-resonance, and lowering their intrinsic inductance and quality factors.
