Prepared by Dr. Marco Dragic, Senior Engineer, Microelectronics, and Jim Quinn, Prototyping Services Engineer, both of CMC Microsystems.
This application note outlines tasks and procedures to prepare your design for fabrication in STMicroelectronics 65-nanometre (nm) CMOS technology, which is supplied through Circuits Multi-Projets (CMP). These steps focus on preparing design layout and are additional to the standard processes required to fabricate any design through CMC (for example, area grant allocation process and packaging request).
This application note provides information for designers on scribe lanes, power rings, process options, logos, black box cells, design rule checking, pattern filling for acceptable layer density, and design submission.
Items available for download include:
- application note, and
- design file
All CMC Microsystem account holders with a Subscription are authorized to access this application note. For more information contact Linda Dougherty at licensing@cmc.ca or 613-530-4787.
