Prepared by Robert Mallard, Manager of Hybrid Packaging and Microsystems Test, CMC Microsystems.
This application note describes design and fabrication considerations for optoelectronic chip carriers, intended for applications in photonic device testing and prototyping. The design of a semiconductor component is highly refined to meet stringent performance requirements. The component’s packaging environment, which includes the carrier, is a critical part of this design and, due to its electrical, optical, thermal and mechanical stress considerations, can have a significant impact on device performance.
All CMC Microsystem account holders with a Subscription are authorized to access this application note. For more information contact Linda Dougherty at licensing@cmc.ca or 613-530-4787.
