Prepared by Dr. Marco Dragic, Senior Engineer, Microelectronics, and Jim Quinn, Prototyping Services Engineer, both of CMC Microsystems.
This application note outlines tasks and procedures to prepare your design for fabrication in the 90-nanometre (nm) CMOS technology from STMicroelectronics (ST), supplied through Circuits Multi-Projects (CMP). These steps focus solely on preparing the design layout and are additional to the standard CMC processes required to fabricate any design through CMC (for example, area grant allocation process, packaging request; etc.). The information is gathered from previous experience in manufacturing designs and serves as a useful guide and checklist.
Items available for download include:
- application note document
- two example files for required steps in the design flow
All CMC Microsystem account holders with a Subscription are authorized to access this application note. For more information contact Linda Dougherty at licensing@cmc.ca or 613-530-4787.
