Prepared by Ruslana Gelman, MSc Candidate, Applied Science and Engineering, University of Toronto.
This application note describes techniques for the following:
- A means of adding microelectrode arrays on CMOS die using gold stud bumping for neural interfacing applications
- Partial encapsulation for controlled die access
- An experimental setup for interfacing brain tissue with the fabricated neural CMOS microsystem
- An initial assessment of the efficacy of stacked stud bumps as neural recording electrodes
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