Design Kit: TSMC 0.35 µm CMOS Process

Design Kit: TSMC 0.35 µm CMOS Process

This design kit is for the 0.35µm CMOS technology from Taiwan Semiconductor Manufacturing Company (TSMC) and includes TSMC cell libraries.

This technology developed by TSMC and provided through CMC's partnership with MOSIS, is a 0.35µm dual poly 4 metal polycide CMOS process. The recommended nominal supply voltage is 3.3 volts. The design kit is suitable for analog mixed-signal and RF designs.

The minimum drawn gate length for this technology is: 0.35 µm.

All CMC Subscribers are authorized to access this technology. Contact the Licensing Administrator at licensing@cmc.ca or 613-530-4787 for more information.


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